An analog-to-digital converter (also known as an ADC or an ND converter) is an electronic circuit that measures a real-world signal (such as temperature, pressure, acceleration, and speed) and converts it to a digital representation of the signal. An ADC compares an analog input to a known reference and produces therefrom a digital representation of this analog input. The output of an ADC is a digital binary code. By its nature, an ADC introduces a quantization error. This is simply the information that is lost, because for a continuous analog signal there are an infinite number of voltages but only a finite number of ADC digital codes. The more digital codes that the ADC can resolve, the more resolution it provides and the less information lost to quantization error.
A Nyquist limit is defined as half of the sampling frequency. The Nyquist limit sets the highest frequency that a system is able to sample without frequency aliasing. In a sampled data system, when the input signal of interest is sampled at a rate slower than the Nyquist limit (fIN>0.5fSAMPLE), the signal is effectively ‘folded back’ into the Nyquist band, thus appearing to be at a lower frequency than it actually is. This unwanted signal is indistinguishable from other signals in the desired frequency band (fSAMPLE/2).
An algorithmic-based nyquist ADC's performance relies on an ability to accurately achieve a times two (×2) gain. For ADC resolutions above 10 bits the ×2 gain is a constraint to a good linearity.
FIG. 1 illustrates a known ratio-independent technique for correcting capacitor mismatch errors within, for example, an ADC amplifier circuit. The design structure of this known technique allows capacitor mismatch cancellation using four clock phases. FIG. 2 illustrates the configuration of the circuitry within each of the four clock cycles (a) to (d). This known technique provides a ratio-independent multiply-by-two switching sequence, whereby an input voltage is sampled in the first clock phase (a); the charge is then transferred in the second clock phase (b); the input voltage is then sampled again the third clock phase (c); and finally the charge is transferred and capacitors exchanged in the fourth clock phase (d).
A problem with this, and other, known techniques, is that it requires a complex switching network, requiring a complex clock scheme. In addition, such techniques require a separate ‘sample & hold’ stage, resulting in increased power consumption and increasing the amount of die space required. Furthermore, the large number of capacitors used for such techniques require a significant amount of die space.
As will be appreciated by a skilled artisan, market demands require not only a reduction in the cost and size of integrated circuits and the like, but also a reduction in their power consumption requirements in order to improve battery performance of device within which such integrated circuits and the like are used.
Thus, a need exists for an improved differential amplifier circuitry in which the above-mentioned problems are substantially alleviated.